Announcements

1. The Cadence Virtuoso Layout Editor Cell-Design Tutorial PDF file is online.
2. Grading Policy (at the bottom) has been updated.
3. Homework assignment links are in place. Each link is to be activated  when the assignment is made.
4. On the textbook: the 3rd Edition of Weste's book is a fine choice and should work with this syllabus.
5. Attendance and homework assignment grades are on the Scoreboard now.
6. EE Unix Laboratory schedule of hours.
7. Project 3 demo schedule is here for sign-ups.

Professor Xinghao Chen
Office: T-502, Steinman Hall
Phone: 212-650-7889
Email: xchen@ccny.cuny.edu

This course presents a systematic approach to the design of full-custom, very and ultra large scale integrated (VLSI and ULSI) circuits, utilizing state-of-the-art electronic design automation (EDA) commercial engineering software – the Cadence Design System. It is to cover three major areas: CMOS Processing Technologies, High-Performance Circuit Design Techniques and Practices, Advanced EDA CAD Software Applications, coupled with design projects.

Principles of CMOS VLSI Design - A System Perspective, Second Edition, by Neil H.E. Weste & Kamran Eshraghian, Addison Wesley, ©1993. ISBN 0-201-53376-6.

Digital Integrated Circuits - A Design Perspective, Second Edition, by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic, Prentice Hall, ©2003, ISBN 0-13-090996-3.

PSpice for Basic Circuit Analysis, by Joseph G. Tront. McGraw-Hill, New York, NY. ©2004. ISBN 0-07-298509-7.

Reference Books

Digital Integrated Circuit Design, Ken Martin, Oxford University Press, ©2000. ISBN 0-19-512584-3.

Digital Design - Principles & Practices, John F. Wakerly, Third Edition Updated, Prentice Hall, ©2001. ISBN 0-13-089896-1.

High Speed CMOS Design Styles, by Kerry Bernstein, Keith M. Carrig, Christopher M. Durham, Patrick R. Hansen, David Hogenmiller, Edward J. Nowak, Norman J. Rohrer, Kluwer Academic Publishers, ©1999, ISBN 0-7923-8220-X.

The Soul of a New Machine, by Tracy Kidder. Little, Brown and Co., Boston, MA. ©1981. ISBN 0-316-49170-5. This book won the Pulitzer Prize.

CMOS Logic Circuit Design, by J. P. Uyenmura. Kluwer Academic Publishers, MA. ©1999. ISBN 0-7923-8452-0.

Introduction to VLSI Circuits and Systems, by J. P. Uyenmura. John Wiley & Sons, New York, NY. ©2002. ISBN 0-13-061970-1.

Modern VLSI Design – System-on-Chip Design, Third Edition, by J. P. Uyenmura. Prentice-Hall, Upper Saddle River, NJ. ©2002. ISBN 0-13-032162-1.

CMOS/BiCMOS ULSI Low Voltage, Low Power, by K. S. Yeo, S. S. Rofail, and W. L. Goh. Prentice-Hall, Upper Saddle river, NJ. ©2002. ISBN 0-13-032162-1.

Analog VLSI and Neural Systems, by Carver. Mead, Addison Wesley,  ISBN 0-201-05992-4.

CMOS Digital Integrated Circuits Analysis and Design, by S. M. Kang and Y. Leblebici. McGraw-Hill, New York, NY. ©1996. ISBN 0-07-038046-5.

Circuits, Interconnections, and Packaging for VLSI, by H. B. Bakoglu. Addison-Wesley, Reading, MA. ©1990. ISBN 0-201-06008-6.

Cadence Design System Manual (on-line with the software package, to be announced).

Wednesday, 6:30-9:15pm, at S-277.

Completed CCNY EE or CpE 4-year undergraduate program requirements.

Monday 3:30-5pm, Wednesday 3:30-4:30pm, at T-502.

TBD

Week 1

    September 1:

• Introduction to IC & Design Technologies
• CMOS Transistor Theory
• Reading: Weste's - Chapter 1 with Sections 1.1-4, Chapter 2 with Sections 2.1-2; Rabaey's - Chapter 1, Chapter 3 with Sections 3.1-3.

    September 8

• The CMOS Inverter
• Noise Margin
• The Wire
• Reading: Weste's - Chapter 2; Rabaey's - Chapters 4 & 5.
• Homework #1: Weste's Chapter 2 Problems: 4, 5, 6, 7, 8, 9.

Week 3

    September 15

• No Class

Week 4

    September 22

• CMOS Processing/Manufacturing Technology.
• Reading: Weste's - Chapter 3; Rabaey's - Chapter 2.
• Homework #1 Review

Week 5

    September 29

• IC Layout & Design Rules.
• Physical Layout Design I - The Manual Way with Stick Diagram and Colored Symbolic Layout.
• Interconnect & Characterization and Performance Estimation.
• Reading: Weste's - Chapters 3, 4 & 5; Rabaey's - Chapters 2, 9 & 10.
• Homework #2: Weste's Charpter 3 Problems: 3, 4, 5, 6, 7, 8.

Week 6

    October 6

• CMOS Combinational Logic Gates.
• Designing Sequential Logic Circuits.
• Reading: Weste's - Chapter 5; Rabaey's - Chapters 6 & 7.

Week 7

    October 13

• Circuit and System Clocking & Timing.
• I/O Structures.
• Designing Arithmetic Circuits I.
• Reading: Weste's - Chapters 5 & 8; Rabaey's - Chapters 10 & 11.
• Homework #3.

Week 8

    October 20

• PSPICE Simulation Demo
• Project #1.

Week 9

    October 27

• Designing Memory & Array Structures.
• Reading: Weste's - Chapter 8; Rabaey's - Chapter 12.
• Homework #4.

Week 10

    November 3

• Cadence Design System Demo & Tutorial
• Physical Layout Design II - The Automated Way with Cadence Design System Software.
• Project #2.

Week 11

    November 10

• Introduction to CMOS Circuit Testing.
• Reading: Weste's - Chapter 7; with supplemental materials.
• Homework #5.

Week 12

    November 17

• Layout Strategies.
• Reading: Rabaey's - Chapter 8.
• Exam
• Project #3

Week 13

    November 24 - No Class (Friday Schedule)

Week 14

    December 1

• Design Verification and Test of Manufactured Circuits.
• Reading: Weste's - Chapter 6; Rabaey's - Inserts G & H.

Week 15

    December 8

• No class. Need help with design project? Stop by T-502.
• Sign-up for Project 3 demo schedule at T-502.

Week 16

    December 14 (Tuesday)

• No class. One-on-one Design Workshop (in T-502).

December 16-22: Design Projects: Show-and-Tell

• Stop by T-502 at your scheduled time. Check your project on EE Unix network before coming.

• Attendance: 5%
• Homework: 30%
• Exam: 20%
• Project 1: 10%
• Project 2: 15%
• Project 3: 20%
• Project 4: 10% (optional)