CREU Project

Project Description

Cache memories have received great attention recently, as evidenced by the fact that
most of the current processors have at least two levels of caches and many have even
three levels, all on-chip. However, most, if not all, the research done in cache memory
hierarchy design assumed that the main memory is accessed only by the cache memory,
which is accessed in turn by the processor. This assumption is not realistic. For instance,
graphics cards, which are available in almost all the computer systems, may also be
accessing the memory. In case of a multiprocessor system, or multi-core chip, all the
processors may need to access the memory simultaneously.

The memory is usually connected to the system bus; therefore there will be a lot of
contention on that bus. Moreover, due to the advances in technology, several processors
may be available on chip, exercising a lot of pressure on the chip pins, as well as on the
system bus. Hence, the cache may want to access the main memory, due to a cache
miss, but the bus may be busy, in which case, the cache has to wait, leading to
performance loss.

The bus traffic has a tremendous effect on the memory hierarchy performance. In this
project, we try to understand the effect of bus traffic on cache hierarchy design, and
whether we can enhance the cache memory hierarchy to be bandwidth-friendly.