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| Fall 2003 | ||
| Topic:
A Unified Approach for Fault Tolerance and Dynamic Power Management
in Real-Time Embedded Systems
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| Topic:
Improving System Performance and Energy-Efficiency by Exploring the
Interactions of Operating Systems in Computer Architecture Design Date: Thursday, December 18, 2003 Time: 11:00 A.M. -12:00 P.M. Room: Steinman Hall, Room T-512 Speaker: Mr. Tao Li Department of Electrical and Computer Engineering University of Texas at Austin ABSTRACT Advance in VLSI technology enables architects to design more and more powerful microprocessors and computer systems. However, emerging computer applications and system software constantly challenge hardware design. Additionally, today's high-complexity design already results in many critical issues, such as the increasingly constrained power budget. The Operating System (OS) which manages both hardware and software resources, constitutes a major software component of today's complex systems implemented with high-end and generalpurpose microprocessors, memory hierarchy and heterogeneous I/O devices. Many modern and emerging workloads (e.g., database, web servers and file/e-mail applications) exercise the OS significantly. Unfortunately, so far, microprocessor performance and power optimizations have been entirely focus on the user-level applications. In this talk, I will present architectural level optimizations to improve performance and energy-efficiency for the OS and emerging applications. In the first part of my talk, I will show how control flow prediction hardware, which is critically to deliver instruction level parallel (ILP) and pipelining performance on today's highly-speculative and deeply-pipelined machine, can be cost-effectively adapted to significantly improve its speculation accuracy on the exception-driven, intermittent OS execution. Experimental results show that incorporating OS-aware adaptations yields up to 34%, 23%, 27% and 9% prediction accuracy improvement on four state-of-the-art branch predictors during the emerging workloads execution. In the second part of my talk, I will address the adaptations of processor resources to reduce OS power on today's high-performance processors, which exploit aggressive hardware design to maximize the performance across a wide range of targeted applications. Current adaptation techniques rely on periodic sampling schemes to match program computational requirement with processor resources. Unfortunately, it becomes difficult to accurately predict and adapt processor resources in a timely fashion for OS power savings without significant performance degradation. I proposed a routine based OS-aware microprocessor resource adaptation scheme that permits precise processor adaptations for the OS with low overhead. Experimental results show that the proposed scheme yields more attractive Energy-Delay tradeoffs on the OS execution than sampling based mechanisms. |
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